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TRF7970A
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
6.4
6.4.1
6.4.2
Receiver – Analog Section
Main and Auxiliary Receivers
The TRF7970A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is
connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is
available on at least one of the two inputs. This architecture eliminates any possible communication holes
that may occur from the tag to the reader.
The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers - the main receiver and the
auxiliary receiver. Only the main receiver is used for reception, the auxiliary receiver is used for signal
quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register
(address 0x00).
After startup, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection,
first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver
is connected to the digitizing stage which output is connected to the digital processing block. The main
receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal
(subcarrier signal).
The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of
the demodulated subcarrier signal (internal RSSI). After startup, RX_IN2 is multiplexed to the auxiliary
receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage
and finally the auxiliary RSSI block.
The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary
receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1)
and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI level register (address
0x0F). The MCU can read the RSSI values from the TRF7970A RSSI register and make the decision if
swapping the input- signals is preferable or not. Setting B3 in Chip Status Control register (address 0x00)
to 1 connects RX_IN1 (pin 8) to the auxiliary received and RX_IN2 (pin 9) to the main receiver. This
mechanism needs to be used to avoid reading holes.
The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and
RX_IN2 should be approximately 3 VPP for a V IN supply level greater than 3.3 V. If the V IN level is lower,
the RF input peak-to-peak voltage level should not exceed the V IN level.
Receiver Gain and Filter Stages
The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The
band-pass filter has programmable 3d-B corner frequencies between 110 kHz to 450 kHz for the high-
pass filter and 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gain-
and-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first band-
pass stage.
The internal filters are configured automatically depending on the selected ISO communication standard in
the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly
to the RX special setting registers (address 0x0A).
The main receiver also has a second receiver gain and digitizer stage which is included in the AGC loop.
The AGC loop is activated by setting the bit B2 = 1 in the Chip Status Control register (0x00). When
activated, the AGC continuously monitors the input signal level. If the signal level is significantly higher
than an internal threshold level, gain reduction is activated.
By default, the AGC window comparator is set after the first 4 pulses of the subcarrier signal. This
prevents the AGC from interfering with the reception of the remaining data packet. In certain situations,
this AGC freeze is not optimal, so it can be removed by setting B0 = 1 in the RX special setting register
(address 0x0A).
20
Detailed Description
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